To manufacture a semiconductor device such as memory or logic, an electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive for conductor and resistor fabrication and can also be of differing conductivity types, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, or conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible.
In this disclosure, "N-type" denotes silicon that has been doped with atoms having more than four valence electrons (group V or higher) such as arsenic or phosphorus which introduce negatively charged majority carriers into the silicon, and "P-type" denotes silicon doped with atoms having less than four valence electrons (group III or lower) such as boron which introduce positively charged majority carriers. The majority charge carrier type is also referred to as conductivity type. "Poly" denotes polycrystalline silicon. By photomasking, geometries on the order of a micron or less are obtainable for device elements in the integrated circuit.
Several process steps are required to produce a functional semiconductor die. A wafer of a starting material such as silicon or gallium arsenide is layered with oxide, poly, nitride, photoresist, and other materials in various configurations, depending on the type and design of the device which is being produced. Each step may require the local deposition of one of the above listed materials (patterning), or a blanket layer of the material may be laid down and a pattern etched away with chemicals or abraded away by particles.
Features having sharp points or asperities 10 on the surface of a substrate 12, as shown in FIG. 1, are used as emitter tips in computer display screen technology. These tips 10 are usually formed by placing a mask 14 on the surface of the substrate 12, and wet or dry etching the substrate surface 12 to undercut the mask 14. A problem with this method of forming the asperities 10 is that the etch time greatly affects the sharpness and uniformity of the tip 10. FIG. 2 shows the results of four different etch times on an asperity. At time "1" the substrate is greatly underetched, and the asperity is nonexistent. At time "2" the asperity approaches the desired shape, but is still slightly underetched. Time "3" produces the desirable point of FIG. 1, while at time "4" the substrate is overetched and the tip is not as sharp. Furthermore, because the etch rate is not uniform across the substrate, it is at best exceedingly difficult to produce a plurality of emitters all having critically sharp characteristics which form simultaneously. U.S. Pat. No. 3,970,887 by Smith, et al., which is incorporated herein by reference, describes the manufacture of emitter tips.